1. Field of the Invention
The invention relates to detection of defects in patterned substrates, such as semiconductor wafers, particularly by inspection using an electron beam.
2. The Prior Art
It is generally accepted that the most economical approach to increasing yields of semiconductor devices is to detect defects as early as possible during fabrication, rather than at final test of the devices. Early detection can allow a source of defects to be identified and eliminated before large numbers of wafers are affected. Thus, it is now standard industry practice to inspect wafers for defects at multiple stages of fabrication.
In-line inspection is now mostly done using optical inspection tools such as the 21XX-series wafer-inspection tools of KLA-Tencor. These employ a high-performance optical microscope, a fast scanning stage, a time-delay-integration, fast-scanning CCD image sensor, and a multi-processor image-processing computer. Algorithms are provided which perform pixel-by-pixel comparison of an optical image of a die against images of one or two neighboring die or dice, or pixel-by-pixel comparison of an optical image of a memory cell against neighboring memory cells. Other optical inspection systems are supplied, for example, by Applied Materials, formerly Orbot, and Hitachi.
Optical tools are inherently limited by diffraction and depth of focus. As a result, more than 50% of killer defects arising in processes using &lt;0.35 .mu.m design rules prove to be optically undetectable defects. Killer defects are defects which adversely affect electrical performance of a device at final test of the device. Trends indicate that this problem will become worse, especially for metal interconnect layers with sub-surface defects. This is due to the small depth of focus of conventional optical inspection tools, an inherent limitation of the large numerical aperture objective lenses required to image sub-micron features. Thus any defect that is not at the device surface will be substantially out of focus and therefore undetectable. Examples of such sub-surface defects include polysilicon gate shorts, open vias and contacts, and metal stringers. All of these result in either an electrical "open" or "short" type defect. Also, diffraction-limited resolution renders small surface defects undetectable as minimum critical dimensions (CDs) shrink below 0.25 .mu.m. These include defects such as .about.0.1 .mu.m particles and regions of missing or extra pattern which are at or below the minimum CD.
Conventional scanning-electron-microscope (SEM) and electron-beam prober technology can image these small surface defects. E-beam probers can also "observe" (detect) sub-surface defects by measuring the voltage-contrast change resulting from the electrical effect of killer defects, i.e., "open" and "short" type defects. See, for example: T. ATON et al, Testing integrated circuit microstructures using charging-induced voltage contrast, J. VAC. SCI. TECHNOL. B 8 (6), November/December 1990, pp. 2041-2044; K. JENKINS et al., Analysis of silicide process defects by non-contact electron-beam charging, 30.sup.TH ANNUAL PROCEEDINGS RELIABILITY PHYSICS 1992, IEEE, March/April 1992, pp. 304-308; J. THONG, ED., ELECTRON BEAM TESTING TECHNOLOGY, Plenum Press 1993, p. 41; and T. CASS, Use of the Voltage Contrast Effectfor the Automatic Detection of Electrical Defects on In-Process Wafers, KLA Yield Management Seminar, pp. 506-2 through 506-11.
Conventional SEMs are too slow, however, to cover a statistically significant wafer area or number of defects in a short enough period of time. This limitation stems primarily from the slow serial nature of the data-collection process, though also in part from a general lack of automation. In addition the time taken to move the mechanical stage to each new imaging position is large compared to the imaging time and thus limits throughput even with automation features.
KLA's SEMSpec system is based on a conventional optical inspection system having a mechanical scanning stage. It uses a continuously-moving, accurate scanning stage together with a high-current beam and a high-bandwidth detector to increase the area-coverage rate. The scanning stage reduces stage-move time as a primary limiting factor in system throughput. The overall area-coverage rate of .about.1 cm.sup.2 /hour with the SEMSpec system is substantially less that the several thousands of cm.sup.2 /hour with fully automated optical tools. See, for example, U.S. Pat. No. 5,502,306 and U.S. Pat. No. 5,578,821 to Meisburger et al.
Co-pending U.S. patent applications Ser. No. 08/782,740 filed Jan. 13, 1997, now abandoned, and Ser. No. 09/012,227 filed Jan. 23, 1998, now U.S. Pat. No. 6,162,621, disclose another approach to obtaining higher rates of area coverage, at least for conductive layers. The conductive layers are pre-charged and then "under-sampled" where features are typically long, thin, co-parallel wires. For example, FIG. 1 illustrates pre-charged 10.times. undersampling of an IC layer 100 having conductors such as 105 and 110 oriented mostly in a single direction. The sanple surface is precharged and only one of ten lines is sampled. Shown at 115 is the e-beam-sampling scan path. The layout of a typical logic IC maximizes routing density by orienting conductors of alternate layers in mutually-orthogonal directions--conductors of one layer are routed mostly in the x-direction while conductors of adjacent layers are routed mostly in the y-direction. The pre-charged, under-sampling approach offers much benefit with layers having characteristics suited to under-sampling. It is unfortunately not as effective with layers having other characteristics, e.g., layers with small features such as vias, contacts, localized interconnects and memory cells. This approach also unlikely to detect small particles or missing or extra pattern.
A result is that, in many situations, e-beam-based defect detection is only feasible with full imaging rather than undersampling. Full-imaging with an area-coverage rate of .about.1 cm.sup.2 /hour would take an estimated .about.270 hours to cover all of a typical 200 mm-diameter wafer. To improve throughput, it is instead desirable to selectively sample areas of the wafer that are expected to have the most defects of interest. It is also advantageous to be able to compare against any reference die, or against a database, rather than against only a neighboring die as is the case with scanning-based optical inspection systems currently in use and with the SEMSpec system.
The ability to compare an image of a die against any reference allows sampling of the wafer area to be targeted at a specific defect distribution. For example, comparing the center die of a wafer, which is more likely to be defect free, with edge dice, which are often expected to have higher defect densities, maximizes the likelihood of detecting such defects. FIG. 2 illustrates a desired sampling scenario tailored for a specific defect distribution, but which is not addressed by prior art systems. In this example a center die 200 of wafer 205 is selected as a reference and is compared to outlying die 210 which are more likely to have defects. Comparing a die to an adjacent die would be less likely to show all the defects.
It is believed that commercially available e-beam defect detection systems only look at memory arrays by comparing one memory cell against its neighbors. While a scanning stage-based system might be used to perform a die to any die comparison, the scanning stage turn-around time would be a primary overhead factor limiting throughput. FIGS. 3A an 3B illustrate the effect of state turn-around time.
FIG. 3A shows the path 300 of a continuously moving stage (not shown) relative to an area 305 of a wafer being scanned. Image data is acquired while the stage is moving at a constant velocity. The average rate of data acquisition is reduced by the time required for the mechanical stage to decelerate, reverse direction, and accelerate to scanning speed, and the time required to realign the beam with the sample. FIG. 3B illustrates the overscan resulting from use of a continuously moving scanning stage. To scan an area 310 of wafer 315 at a constant velocity, the stage must move beyond the edge of the scanned area 310 for deceleration, reversal, and acceleration. The scan path of the stage relative to area 310 is shown at 320.
A goal for a charged-particle-beam defect-detection system to be used in a production environment is to minimize or eliminate stage overhead so that acquisition speed is limited by the fundamental physics of the beam, thus taking best advantage of charged-particle beam technology to detect optically undetectable defects (OUDs).
In general, a wide range of potential reference image sources can be used, each having relative advantages and disadvantages in specific applications. The most versatile approach is to have complete flexibility in sampling and choice of reference without compromising throughput. Presently available systems lack such flexibility. Following is a description of some desired comparisons.
Comparison Comments Cell to Cell Typically used for memory cells. A perfect reference cell may be used to compare to every cell in a memory array, or each memory cell (or repeating structure such as a block of 2 or 4 symmetrically-reflected cells) is compared with its neighbor. Die to die This is typically a standard mode of operation for an optical inspection system such as the KLA213X. Each die is compared to its adjacent neighbor during the scanning process. A third die is then used to arbitrate which die actually has the defect. This works well for random defects but not for repeating defects such as extra pattern in a tightly-routed section of the mask. In general, it is preferred to have the capability to efficiently compare any die with any die, using any third die for arbitration. Die to any die comparisons are valuable because the user can target specific areas of the wafer with a particular expected defect type and compare against a die that is likely to be good. Edge die to center die comparison on a semiconductor wafer is desirable for this reason, since edge die are often "weak" and less likely to yield than center die. Die to golden die An image or other data from a known-good reference die ("golden" die) on another wafer is stored in memory and compared to the die under inspection. A large volume of data is required, literally hundreds of gigabytes, but disk and memory space is becoming less costly and there is potential for image compression of voltage contrast images. No arbitration is required when comparing with a "golden" die. Die to database This technique is known for inspection of masks, such as in KLA's mask inspection systems. A challenge with the apparent-feature enlargement approach is that multiple layers of the database and knowledge of the electrical properties of the circuit represented are required to determine which features are grounded and which are floating in negative charge mode, e.g., which p-n junctions are forward biased by the negative potential or voltage. Block to block Similar to die to die but just some subsection(s) of the die are compared. This is useful when a portion of the die is known or expected to be more likely to have a particular type of defect of interest. This approach saves time over full die-to-die comparison.
Conventional SEM columns are optimized for best imaging performance for a relatively small Field of View (FOV), typically within 1 .mu.m to 100 .mu.m of the column's optical axis. Mechanical stages move the sample wafer and column relative to one another to allow viewing of the complete sample. This is acceptable in applications where throughput is not a major concern, and is believed to be the norm in commercial SEMs. Particle-beam systems are known to operate over a large field of view (FOV) for purposes such as e-beam lithography, but not for defect detection. See, for example, H. PFEIFFER, Recent Advances in Electron-Beam Lithographyfor the High-Volume Production of VLSI Devices, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-26, No. 4, April 1979; and N. SAITOU et al, Variably shaped electron beam lithography system, EB55: II ELECTRON OPTICS, J. VAC. SCI. TECHNOL., 19(4), November/December 1981. It is also known to use a large FOV for overlay alignment, as in U.S. Pat. No. 5,401,972 to Talbot et al. and in Schlumberger's commercially-available IDS P2X and AMS systems.
Improved systems and methods are needed for detection of defects on a patterned substrate.